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ds05-30336-2e fujitsu semiconductor data sheet memory flash memory card pcmcia rel.2/jeida ver.4 conformable MB98A809Bx-/810bx-/811bx-/812bx- 25 flash erasable and programmable memory card 512 k/1 m/2 m/4 m-byte n description the fujitsu MB98A809Bx, mb98a810bx, mb98a811bx and mb98a812bx are flash electrically erasable and programmable (flash) memory cards capable of storing and retrieving large amounts of data. the memory circuits are housed in a credit-card sized 68-pin package. internal circuit is protected by two metal panels, one at the top and bottom of the card, that help to reduce chip damage from electrostatic discharge. a unique feature of the fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus con?uration. all cards are portable and operate on low power at high speed. in accordance with the personal computer memory card international association (pcmcia) and japan electrical industry development association (jeida) industry standard speci?ation, flash memory cards offer additional eeprom memory that is used to store attribute data. the attribute memory is a flash memory card option. (see page 3 for description of the three available options.) credit card size: 85.6 mm (length) 54.0 mm (width) 3.3 mm (thick) pcmcia/jeida conformed two-piece 68-pin connector (with a two-row built-in receptacle) single +5.0 v 5% power supply (+12.0 v 5%v pp ) command control for write/erase operation write protect function n package crd-68p-m17
2 MB98A809Bx-/810bx-/811bx-/812bx- 25 n attribute memory options pcmcia and jeida standard memory cards from fujitsu provide a separate eeprom memory address space for recording fundamental card information. it is used by the card manufacturers to record basic con?uration information such as device type, size, speed, etc. the attribute memory is selected by asserting the reg pin on the card interface. option descriptions as follows: option 1: attribute memory is not supported. reg pin: not contacted (jeida ver.3 conformable) option 2: attribute memory in a separate location is not supported. when reg line is asserted, ?f?is output to the data bus to indicate that attribute data may be stored in main memory. (pcmcia rel.2/jeida ver.4 conformable) option 3: attribute memory is supported. the data is stored in 16 k-bit eeprom. when the reg line is asserted, data stored in eeprom is output to the data bus. (pcmcia rel.2/jeida ver.4 conformable) * : to be con?ured by user. part number main memory attribute memory memory organization * memory device access time memory device access time MB98A809B1 2 m flash memory 2 pcs 250 ns 512 k 8 bits/256 k 16 bits mb98a810b1 2 m flash memory 4 pcs 250 ns 1 m 8 bits/512 k 16 bits mb98a811b1 2 m flash memory 8 pcs 250 ns 2 m 8 bits/1 m 16 bits mb98a812b1 2 m flash memory 16 pcs 250 ns 4 m 8 bits/2 m 16 bits part number main memory attribute memory memory organization * memory device access time memory device access time MB98A809B2 2 m flash memory 2 pcs 250 ns 512 k 8 bits/256 k 16 bits mb98a810b2 2 m flash memory 4 pcs 250 ns 1 m 8 bits/512 k 16 bits mb98a811b2 2 m flash memory 8 pcs 250 ns 2 m 8 bits/1 m 16 bits mb98a812b2 2 m flash memory 16 pcs 250 ns 4 m 8 bits/2 m 16 bits part number main memory attribute memory memory organization * memory device access time memory device access time MB98A809B3 2 m flash memory 2 pcs 250 ns eeprom 1 pcs 300 ns 512 k 8 bits/256 k 16 bits mb98a810b3 2 m flash memory 4 pcs 250 ns eeprom 1 pcs 300 ns 1 m 8 bits/512 k 16 bits mb98a811b3 2 m flash memory 8 pcs 250 ns eeprom 1 pcs 300 ns 2 m 8 bits/1 m 16 bits mb98a812b3 2 m flash memory 16 pcs 250 ns eeprom 1 pcs 300 ns 4 m 8 bits/2 m 16 bits
3 MB98A809Bx-/810bx-/811bx-/812bx- 25 ce 0 ce 15 a 0 a 1 bvd1 bvd2 d 0 18 8 8 gnd v cc d 15 2 mb flash memory 1 (MB98A809Bx) 2 (mb98a810bx) 4 (mb98a811bx) 8 (mb98a812bx) internal circuit r 1 = 10 k w r r = 100 k w fig. 1 ? MB98A809Bx, 810bx, 811bx, and 812bx block diagram 11 r r r 16k eeprom *1 input decoder & buffer i/o trans- ceiver & buffer v cc add add i/o i/o notes: *1. eeprom is only available in option 3 (for attribute memory) flash memory cards. *2. see pins 48, 49, and 50 in ?in assignments. *3. n.c. terminal in mb98a8xxb1 series. add i/o v pp v pp v pp1 v pp2 1 (MB98A809Bx) 2 (mb98a810bx) 4 (mb98a811bx) 8 (mb98a812bx) a 19 * 2 a 20 * 2 a 21 * 2 wp r r 2 mb flash memory wp.sw we oe ce 1 ce 2 cd 1 cd 2 we oe ce we oe ce oe we cs reg *3 a 18 c 1
4 MB98A809Bx-/810bx-/811bx-/812bx- 25 n pin assignments * : n.c. terminal in mb98a8xxb1 series. MB98A809Bx mb98a810bx mb98a811bx mb98a812bx pin no. MB98A809Bx mb98a810bx mb98a811bx mb98a812bx gnd gnd gnd gnd 1 35 gnd gnd gnd gnd d 3 d 3 d 3 d 3 2 36 cd 1 cd 1 cd 1 cd 1 d 4 d 4 d 4 d 4 3 37 d 11 d 11 d 11 d 11 d 5 d 5 d 5 d 5 4 38 d 12 d 12 d 12 d 12 d 6 d 6 d 6 d 6 5 39 d 13 d 13 d 13 d 13 d 7 d 7 d 7 d 7 6 40 d 14 d 14 d 14 d 14 ce 1 ce 1 ce 1 ce 1 7 41 d 15 d 15 d 15 d 15 a 10 a 10 a 10 a 10 8 42 ce 2 ce 2 ce 2 ce 2 oe oe oe oe 9 43 n.c. n.c. n.c. n.c. a 11 a 11 a 11 a 11 10 44 n.c. n.c. n.c. n.c. a 9 a 9 a 9 a 9 11 45 n.c. n.c. n.c. n.c. a 8 a 8 a 8 a 8 12 46 a 17 a 17 a 17 a 17 a 13 a 13 a 13 a 13 13 47 a 18 a 18 a 18 a 18 a 14 a 14 a 14 a 14 14 48 n.c. a 19 a 19 a 19 we we we we 15 49 n.c. n.c. a 20 a 20 n.c. n.c. n.c. n.c. 16 50 n.c. n.c. n.c. a 21 v cc v cc v cc v cc 17 51 v cc v cc v cc v cc v pp1 v pp1 v pp1 v pp1 18 52 v pp2 v pp2 v pp2 v pp2 a 16 a 16 a 16 a 16 19 53 n.c. n.c. n.c. n.c. a 15 a 15 a 15 a 15 20 54 n.c. n.c. n.c. n.c. a 12 a 12 a 12 a 12 21 55 n.c. n.c. n.c. n.c. a 7 a 7 a 7 a 7 22 56 n.c. n.c. n.c. n.c. a 6 a 6 a 6 a 6 23 57 n.c. n.c. n.c. n.c. a 5 a 5 a 5 a 5 24 58 n.c. n.c. n.c. n.c. a 4 a 4 a 4 a 4 25 59 n.c. n.c. n.c. n.c. a 3 a 3 a 3 a 3 26 60 n.c. n.c. n.c. n.c. a 2 a 2 a 2 a 2 27 61 reg /n.c.* reg /n.c.* reg /n.c.* reg /n.c.* a 1 a 1 a 1 a 1 28 62 bvd2 bvd2 bvd2 bvd2 a 0 a 0 a 0 a 0 29 63 bvd1 bvd1 bvd1 bvd1 d 0 d 0 d 0 d 0 30 64 d 8 d 8 d 8 d 8 d 1 d 1 d 1 d 1 31 65 d 9 d 9 d 9 d 9 d 2 d 2 d 2 d 2 32 66 d 10 d 10 d 10 d 10 wp wp wp wp 33 67 cd 2 cd 2 cd 2 cd 2 gnd gnd gnd gnd 34 68 gnd gnd gnd gnd
5 MB98A809Bx-/810bx-/811bx-/812bx- 25 n pin descriptions n pin locations symbol pin name input/output function a 0 to a 21 address input input address inputs, a 0 to a 21 . d 0 to d 15 data input/output input/output data inputs/outputs. this data bus size (8-bit or 16-bit) is selected with ce 1 and ce 2 . ce 1 card enable for lower byte input active low. - lower byte (d 0 to d 7 ) is selected for read/write/ erase function of ?sh memory cards. ce 2 card enable for upper byte input active low. - upper byte (d 8 to d 15 ) is selected for read/write / erase function of ?sh memory cards. reg attribute memory select input active low. - attribute memory is selected for read/write function of identi?ation data of ?sh memory cards. (n.c. or ?f data or attribute data.) oe output enable input active low. - output enable for ?sh memory cards. we write enable input active low. - write enable for ?sh memory cards. v pp1 programming voltage 1 input programming voltage for lower byte. v pp2 programming voltage 2 input programming voltage for upper byte. cd 1 , cd 2 card detect output these pins detect if the card has been correctly inserted. both pins are tied to gnd internally. wp write protect output write controller for ?sh memory cards. this pin outputs the protect/non protect status of ?p switch? bvd1, bvd2 battery voltage detect output both pins are tied to v cc internally. v cc power supply power supply voltage. (+5.0 v 5%) gnd ground system ground. n.c. non connection 34 68 1 35 front side back side fig. 2 ? bottom view (connector side)
6 MB98A809Bx-/810bx-/811bx-/812bx- 25 n functional truth table main memory function *1 read function (reg = v ih ) erase/write/verify function (reg = v ih ) notes: *1. h = v ih , l = v il , x = either v il or v ih , wp sw = write protect switch, p = protect, np = non protect *2. l-level is output when wpsw = np. h-level is output when wpsw = p. *3. v ppl is recommended though it is functionable at v pph . ce 2 ce 1 a 0 oe we wp *2 v pp2 v pp1 mode data input/output wp sw d 8 to d 15 d 0 to d 7 h h xxx x v ppl v ppl standby high-z p or np hlllh x v ppl v ppl read ( 8) high-z d out (lower byte) p or np h l hlh x v ppl v ppl read ( 8) high-z d out (upper byte) p or np lhxlh x v ppl v ppl read ( 8) d out (upper byte) high-z p or np llxlh xv ppl v ppl read ( 16) d out p or np xxxhh x v ppl v ppl output disable high-z p or np ce 2 ce 1 a 0 oe we wp *2 v pp2 v pp1 mode data input/output wp sw d 8 to d 15 d 0 to d 7 h h xxx x v pph v pph standby high-z p or np hlllh l v ppl *3 v pph read ( 8) high-z d out np h l hlh l v pph v ppl *3 read ( 8) high-z d out np h l lhl l v ppl *3 v pph write ( 8) high-z d in np hlhhl l v pph v ppl *3 write ( 8) high-z d in np lhxlh l v pph v ppl *3 read ( 8) d out high-z np lhxhl l v pph v ppl *3 write ( 8) d in high-z np llxlh lv pph v pph read ( 16) d out np llxhl lv pph v pph write ( 16) d in np xxxhh l v pph v pph output disable high-z np
7 MB98A809Bx-/810bx-/811bx-/812bx- 25 attribute memory function *1 (reg = v il ) *2 notes: *1. h = v ih , l = v il , x = either v il or v ih , wp sw = write protect switch, p = protect, np = non protect *2. n.c. for MB98A809B1, 810b1, 811b1, and 812b1. *3. h-level is output for MB98A809B2, 810b2, 811b2, and 812b2. ce 2 ce 1 a 0 oe we wp mode data input/output wp sw d 15 to d 8 d 7 to d 0 h h x x x l standby high-z np h l l l h l read ( 8) high-z d out *3 (lower byte) np hlhlhl read ( 8) high-z h np h l l h l l write ( 8) high-z d in (lower byte) np h l h h l l write ( 8) high-z x np l h x l h l read ( 8) h high-z np l h x h l l write ( 8) high-z high-z np l l x l h l read ( 16) h d out *3 (lower byte) np l l x h l l write ( 16) x d in (lower byte) np x x x h h l output disable high-z np h h x x x h standby high-z p h l l l h h read ( 8) high-z d out *3 (lower byte) p hlhlhh read ( 8) high-z h p hllhlh output disable high-z p h l h h l h output disable high-z p l h x l h h read ( 8) h high-z p l h x h l h output disable high-z p l l x l h h read ( 16) h d out *3 (lower byte) p l l x h l h output disable high-z p x x x h h h output disable high-z p
8 MB98A809Bx-/810bx-/811bx-/812bx- 25 n write/erase chip decoding information note: h = v ih , l = v il , x = either v ih or v il bus organization ce 2 ce 1 a 20 a 19 a 18 a 0 decode chips 8-bit bus hl l l l l chip 0 h chip 1 h l chip 2 h chip 3 h l l chip 4 h chip 5 h l chip 6 h chip 7 h l l l chip 8 h chip 9 h l chip 10 h chip 11 h l l chip 12 h chip 13 h l chip 14 h chip 15 lh l l l x chip 1 h chip 3 h l chip 5 h chip 7 h l l chip 9 h chip 11 h l chip 13 h chip 15 16-bit bus l l l l l x chip 0, chip 1 h chip 2, chip 3 h l chip 4, chip 5 h chip 6, chip 7 h l l chip 8, chip 9 h chip 10, chip 11 h l chip 12, chip 13 h chip 14, chip 15
9 MB98A809Bx-/810bx-/811bx-/812bx- 25 n command definition table command table for 8-bit mode command table for 16-bit mode notes: *1. bus operations are de?ed in ?unctional truth table? *2. ia = identi?r address: 00h for manufacturer code, 01h for device code. ea = address of memory location to be read during erase verify. ra = read address wa = address of memory location to be written. za = address of 256 k-byte zones involved in erase operation. addresses are latched on the falling edge of the write enable pulse. *3. id = data read from location ia during device identi?ation. manufacturer = 31h for 8-bit, 3131h for 16-bit/device = bdh for 8-bit, bdbdh for 16-bit evd = data read from location ea during erase verify. wd = data to be programmed at location wa. data is latched on the rising edge of write enable. wvd = data read from location wa during write verify. wa is latched on the write command. *4. following the read intelligent id command, two read operations access manufacturer and device codes. *5. ?rase flowchart in fig.6, fig.7 and fig.8 illustrate the erase algorithm. *6. ?rite flowchart in fig.4 and fig.5 illustrate the write algorithm. *7. the second bus cycle must be followed by the desired command register write. *8. the reset command operates on a zone basis. to reset the entire card requires reset write cycles to each zone. command bus cycle required first bus cycle second bus cycle operation *1 address *2 data *3 operation *1 address *2 data *3 read memory 1 write ra 00h read intelligent id codes *4 3 write ia 90h read set up erase/erase *5 2 write za 20h write za 20h erase verify *5 2 write ea a0h read ea evd set up write/write *6 2 write wa 40h write wa wd write verify *6 2 write wa c0h read wa wvd reset *7 *8 2 write za ffh write za ffh command bus cycle required first bus cycle second bus cycle operation *1 address *2 data *3 operation *1 address *2 data *3 read memory 1 write ra 0000h read intelligent id codes *4 3 write ia 9090h read set up erase/erase *5 2 write za 2020h write za 2020h erase verify *5 2 write ea a0a0h read ea evd set up write/write *6 2 write wa 4040h write wa wd write verify *6 2 write wa c0c0h read wa wvd reset *7 *8 2 write za ffffh write za ffffh
10 MB98A809Bx-/810bx-/811bx-/812bx- 25 n address configurations *1 (main memory) 8-bit bus organization (ce 1 = v il , ce 2 = v ih ) 8-bit bus organization (ce 1 = v ih , ce 2 = v il ) *2 16-bit bus organization (ce 1 = v il , ce 2 = v il ) notes: *1. h = v ih , l = v il , x = either 0 or 1. *2. even addresses are not available in this mode. a 21 to a 0 ce 2 ce 1 d 15 to d 8 d 7 to d 0 00 00 00 00 11 11 11 11 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0001 0010 0011 1100 1101 1110 1111 h h h h h h h h l l l l l l l l ???? ???? ???? ???? ???? ???? ???? ???? 4,194,300 add. 4,194,301 add. 4,194,302 add. 4,194,303 add. a 21 to a 0 ce 2 ce 1 d 15 to d 8 d 7 to d 0 00 00 00 00 11 11 11 11 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 000x 001x 010x 011x 100x 101x 110x 111x l l l l l l l l h h h h h h h h 4,194,297 add. 4,194,299 add. 4,194,301 add. 4,194,303 add. ???? ???? ???? ???? ???? ???? ???? ???? a 21 to a 0 ce 2 ce 1 d 15 to d 8 d 7 to d 0 00 00 00 00 11 11 11 11 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 000x 001x 010x 011x 100x 101x 110x 111x l l l l l l l l l l l l l l l l 4,194,297 add. 4,194,299 add. 4,194,301 add. 4,194,303 add. 4,194,296 add. 4,194,298 add. 4,194,300 add. 4,194,302 add. 0 add. 1 add. 2 add. 3 add. 1 add. 3 add. 5 add. 7 add. 1 add. 3 add. 5 add. 7 add. 0 add. 2 add. 4 add. 6 add.
11 MB98A809Bx-/810bx-/811bx-/812bx- 25 n absolute maximum ratings (see warning) note: *1. minimum dc input voltage is ?.5 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the device? electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter note symbol value unit supply voltage v cc ?.5 to +6.0 v input voltage v in ?.5 to v cc +0.5 v output voltage v out ?.5 to v cc +0.5 v programming voltage *1 v pp1 , v pp2 ?.0 to +14.0 v storage temperature at turning on the power t bias ?0 to 70 c ambient temperature t a 0 to +60 c storage temperature t stg ?0 to +70 c parameter symbol min. typ. max. unit v cc supply voltage v cc 4.75 5.0 5.25 v ground gnd 0 v ambient temperature t a 0 +55 c
12 MB98A809Bx-/810bx-/811bx-/812bx- 25 n capacitance (t a = 25 c, f = 1 mhz, v in = v i/o = gnd) notes: *1. this value does not apply to ce 1 , ce 2 , we and reg . *2. this value does not apply to ce 1 , ce 2 , bvd1 and bvd2. parameter notes symbol min. max. unit input capacitance *1 c in ?0pf i/o capacitance *2 c i/o ?0pf fig. 3 ? ac test conditions input pulse levels: 0.6 v to 2.6 v input pulse rise and fall times: 5 ns (transient between 0.8 v and 2.4 v) timing reference levels input: v il = 0.8 v, v ih = 2.4 v output: v ol = 0.8 v, v oh = 2.0 v * including jig and stray capacitance ? output load +5 v r1 r2 c l d out (i/o) r1 r2 c l parameter measured load i 1.8 k w 990 w 100 pf all parameters except t clz , t olz , t ehqz , t df , t rclz , t rolz , t rchz and t rohz load ii 1.8 k w 990 w 5 pf t clz , t olz , t ehqz , t df , t rclz , t rolz , t rchz and t rohz
13 MB98A809Bx-/810bx-/811bx-/812bx- 25 n dc characteristics notes: *1. this value does not apply to ce 1 , ce 2 , we and reg . *2. this value does not apply to bvd1, bvd2, cd 1 and cd 2 . *3. this value apply to v pp1 and v pp2 . *4. this value does not apply to bvd1 and bvd2. *5. write/erase are inhibited when v pp = v ppl . parameter notes symbol condition value unit min. typ. max. input leakage current *1 i li v cc = v cc max v in = 0 v or v cc 1.0 20 m a output leakage current *2 i lo v cc = v cc max v in = 0 v or v cc 1.0 20 m a v cc standby current i sb1 v cc = v cc max ce 1 = ce 2 = v cc ?.2 v 0.9 1.7 ma i sb2 v cc = v cc max ce 1 = ce 2 = v ih 7.0 140. ma v cc active read current i cc1 v cc = v cc max ce 1 = ce 2 = v il cyc. = 250 ns, i out = 0 ma 70 100 ma v cc write current i cc2 write in progress 2.0 20 ma v cc erase current i cc3 erase in progress 10 30 ma v pp leakage current *3 i pps v pp v cc 250 m a v pp read current or standby current *3 i pp1 v pp > v cc 0.9 1.8 ma v pp v cc 250 ma v pp write current *3 i pp2 v pp = v pph write in progress 9 30 ma v pp erase current *3 i pp3 v pp = v pph erase in progress 7 30 ma input low voltage v il ?.3 0.8 v input high voltage v ih 2.4 v cc +0.3 v output low voltage v ol i ol = 3.2 ma, v cc = v cc min 0.4 v output high voltage *4 v oh i oh = ?.0 ma, v cc = v cc min 3.8 v v pp during read-only operation *5 v ppl 0 6.5 v v pp during write/erase operation v pph 11.4 12.6 v
14 MB98A809Bx-/810bx-/811bx-/812bx- 25 n ac characteristics (at recommended operating conditions unless otherwise noted.) main memory read cycle *1 attribute memory read cycle *1*4 notes: *1. rise/fall time < 5 ns. *2. transition is measured at the point of 500 mv from steady state voltage. this parameter is speci?d using load ii in fig.3. *3. this parameter is speci?d from the rising edge of oe , ce 1 and ce 2 , whichever occurs ?st. *4. this parameter is for MB98A809B3, 810b3, 811b3, and 812b3. parameter notes symbol min. max. unit read cycle time t rc 250 ns card enable access time t ce 250 ns address access time t acc 250 ns output enable access time t oe 120 ns card enable to output in low-z *2 t clz 5ns card disable to output in high-z *2 t ehqz ?0ns output enable to output in low-z *2 t olz 5ns output disable to output in high-z *2 t df ?0ns output hold from address, ce , or oe change *3 t oh 5ns parameter notes symbol min. max. unit read cycle time t rrc 300 ns address access time t raa 300 ns card enable access time t rce 300 ns output enable access time t roe 150 ns output hold from address change t roh 5ns card enable to output low-z *2 t rclz 5ns output enable to output low-z *2 t rolz 5ns card enable to output high-z *2 t rchz ?0ns output enable to output high-z *2 t rohz ?0ns
15 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory read cycle timing diagram (we = v ih , reg = v ih ) note: *1. a 0 = either v ih or v il . read cycle 1: ce 1 = oe = v il , ce 2 = v ih : 8-bit bus organization address (a 0 to a 21 ) d 0 to d 7 previous data valid data valid t acc t oh v ih v il v oh v ol previous data valid data valid read cycle 2: ce 1 = v ih , ce 2 = oe = v il : 8-bit bus organization ce 1 = ce 2 = oe = v il : 16-bit bus organization address * 1 (a 1 to a 21 ) d 8 to d 15 or d 0 to d 15 t acc t oh v ih v il v oh v ol : undefined t rc t rc
16 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory read cycle timing diagram (we = v ih , reg = v ih ) read cycle 3: ce 2 = v ih : 8-bit bus organization : undefined oe ce 1 address (a 0 to a 21 ) high-z data valid t acc t oe v ih v il v oh v ol t ce v ih v il v ih v il t oh d 0 to d 7 t rc t clz t olz t ehqz t df
17 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory read cycle timing diagram (we = v ih , reg = v ih ) note: *1. a 0 = either v il or v ih . read cycle 4: ce 1 = v ih : 8-bit bus organization : undefined oe ce 1 = ce 2 oe ce 2 t df high-z data valid d 8 to d 15 address *1 (a 1 to a 21 ) t acc t oe v ih v il v oh v ol t ce v ih v il v ih v il t oh t rc t clz t olz t ehqz high-z data valid d 0 to d 15 address *1 (a 1 to a 21 ) t acc t oe v ih v il v oh v ol t ce v ih v il v ih v il t oh t rc t clz t olz t ehqz t df read cycle 5: ce 1 = ce 2 = v il : 16-bit bus organization
18 MB98A809Bx-/810bx-/811bx-/812bx- 25 attribute memory read cycle timing diagram (we = v ih , reg = v il ) *1 notes: *1. this timing diagram is for MB98A809B3, 810b3, 811b3, and 812b3. ?f data is available on MB98A809B2, 810b2, 811b2, and 812b2 only. *2. a 0 = either v ih or v il during 16 bits bus organization. *3. h-level is output from d 8 to d 15 . read cycle 1: ce 1 = oe = v il , ce 2 = v ih : 8-bit bus organization ce 1 = ce 2 = oe = v il : 16-bit bus organization : undefined oe ce 1 previous data valid data valid address * 2 (a 0 to a 11 ) d 0 to d 7 or d 0 to d 15 *3 t raa t roh v ih v il v oh v ol t rrc high-z data valid d 0 to d 7 address (a 0 to a 11 ) t raa t roe v ih v il v oh v ol t rce v ih v il v ih v il t rohz t rrc t rclz t rolz t rchz t roh read cycle 2: ce 2 = v ih : 8-bit bus organization
19 MB98A809Bx-/810bx-/811bx-/812bx- 25 attribute memory read cycle timing diagram (we = v ih , reg = v il ) *1 notes: *1. this timing diagram is for MB98A809B3, 810b3, 811b3, and 812b3. ?f data is available on MB98A809B2, 810b2, 811b2, and 812b2 only. *2. a 0 = either v ih or v il . *3. h-level is output from d 8 to d 15 . read cycle 3: ce 1 = ce 2 : 16-bit bus organization : undefined oe ce 1 = ce 2 d 0 to d 7 * 3 high-z data valid address * 2 (a 1 to a 11 ) t raa t roe v ih v il v oh v ol t rce v ih v il v ih v il t rohz t rrc t rclz t rolz t rchz t roh
20 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write/erase cycle *1 notes: *1. read timing parameters during write/erase operations are the same as during read only operations. refer to ac characteristics for main memory read cycle. *2. rise/fall time 5 ns. *3. the integrated stop timer terminates the write/erase operations, thereby eliminating the need for a maximum speci?ation. parameter notes symbol min. max. unit write cycle time t wc 250 ns address set up time t as 0ns address hold time t ah 100 ns data set up time t ds 80 ns data hold time t dh 30 ns write recovery time before read t whgl 6 m s read recovery time before write t ghwl 0 m s card enable set up time before write t cs 40 ns card enable hold time t ch 0ns write enable pulse width t wp 100 ns write enable pulse width high t wph 60 ns write enable set up time t ws 0ns write enable hold time t wh 0ns card enable pulse width t cp 140 ns card enable pulse width high t cph 60 ns duration of write operation *3 t whwh1 10 m s duration of erase operation *3 t whwh2 9.5 ms v pp set up time to chip enable low t vpel 1.0 m s
21 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write/erase performance *1 notes: *1. excludes 00h writing prior to erasure. *2. t a = 25 c, v pp = 12 v, 100,000 cycles. attribute memory write cycle *1 note: *1. this parameter is for MB98A809B3, 810b3, 811b3, and 812b3. rating notes min. typ. max. unit chip erase time *1 2.0 *2 30 sec. chip write time 4.0 *2 25 *3 sec. write/erase cycle 100,000 100,000 cycle parameter symbol min. max. unit write cycle time t rwr ?0ms address set up time t ras 20 ns card enable set up time t rcs 0ns output enable set up time t roes 20 ns write pulse width t rwp 100 ns address hold time t rah 50 ns data set up time t rds 50 ns data hold time t rdh 20 ns card enable hold time t rch 0ns output enable hold time t roeh 20 ns write recovery time t rre 50 ns end of write to output time t rrbo 100 ns number of write per byte n 10000 times write enable hold time t rweh 10 ns
22 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write cycle timing diagram (we = controlled) *1 note: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. program command latch address & data pro- gram- ming program verify command program verify setup program command data i n = 40h data i n data i n = c0h t wc t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh1 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t oh high-z t clz t ce t vpel valid data we oe ce 1 v ih v il address (a 1 to a 18 ) v ih v il v ih v il v ih v il v ih v il d 0 to d 7 v ppl v pp address (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il t wp t olz write cycle 1: ce 2 = v ih : 8-bit bus organization : undefined
23 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write cycle timing diagram (we = controlled) *1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . program command latch address & data pro- gram- ming program verify command program verify setup program command data i n = 40h data i n data i n = c0h t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh1 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il address (a 1 to a 18 ) v ih v il v ih v il v ih v il v ih v il d 8 to d 15 v ppl v pp address*2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il t wp t wc write cycle 2: ce 1 = v ih : 8-bit bus organization : undefined
24 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write cycle timing diagram (we = controlled) *1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . program command latch address & data pro- gram- ming program verify command program verify setup program command data i n = 4040h data i n data i n = c0c0h t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh1 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1 = ce 2 v ih v il address (a 1 to a 18 ) v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il t wp t wc d 0 to d 15 write cycle 3: ce 1 = ce 2 : 16-bit bus organization : undefined
25 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write cycle timing diagram (ce = controlled) *1 note: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. data i n = 40h data i n data i n = c0h program command latch address & data pro- gram- ming program verify command program verify t wc t wc t wc t ah t as t rc setup program command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh1 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t oh high-z t clz t ce t vpel valid data we oe ce 1 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il address (a 1 to a 18 ) d 0 to d 7 write cycle 4: ce 2 = v ih : 8-bit bus organization : undefined t olz
26 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write cycle timing diagram (ce = controlled) *1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . data i n = 40h data i n data i n = c0h program command latch address & data pro- gra- ming program verify command program verify t wc t wc t wc t ah t as t rc setup program command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh1 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address *2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il address (a 1 to a 18 ) d 8 to d 15 write cycle 5: ce 1 = v ih : 8-bit bus organization : undefined
27 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory write cycle timing diagram (ce = controlled) *1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . data i n = 4040h data i n data i n = c0c0h program command latch address & data pro- gram- ming program verify command program verify t wc t wc t wc t ah t as t rc setup program command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh1 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1 = ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il address (a 1 to a 18 ) d 0 to d 15 write cycle 6: ce 1 = ce 2 : 16-bit bus organization : undefined
28 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory erase cycle timing diagram (we = controlled) *1 note: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. data i n = 20h data i n = 20h data i n = a0h erase command erasing erase verify command erase verify t wc t wc t wc t ah t as t rc setup erase command t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh2 t whgl t wp t dh t dh t wp t wp t chz t oe t dh t ds t ds t ds t olz t oh t clz t ce t vpel valid data ce 1 oe we v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il high-z t ohz address (a 1 to a 18 ) d 0 to d 7 erase cycle 1: ce 2 = v ih : 8-bit bus organization : undefined
29 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory erase cycle timing diagram (we = controlled) * 1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . erase command erasing erase verify command erase verify setup erase command data i n = 20h data i n = 20h data i n = a0h t wc t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh2 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il t wp address (a 1 to a 18 ) d 8 to d 15 erase cycle 2: ce 1 = v ih : 8-bit bus organization : undefined
30 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory erase cycle timing diagram (we = controlled) *1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . erase command erasing erase verify command erase verify setup erase command data i n = 2020h data i n = 2020h data i n = a0a0h t wc t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh2 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il t wp address (a 1 to a 18 ) d 0 to d 15 erase cycle 3: ce 1 = ce 2 : 16-bit bus organization : undefined ce 1 = ce 2
31 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory erase cycle timing diagram (ce = controlled) *1 note: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. erase command erasing erase verify command erase verify setup erase command data i n = 20h data i n = 20h data i n = a0h t wc t wc t wc t ah t as t rc t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh2 t whgl t ohz t cp t dh t dh t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data ce 1 oe we v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il t cp address (a 1 to a 18 ) d 0 to d 7 erase cycle 4: ce 2 = v ih : 8-bit bus organization : undefined
32 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory erase cycle timing diagram (ce = controlled) *1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . data i n = 20h data i n = 20h data i n = a0h erase command erasing erase verify command erase verify t wc t wc t wc t ah t as t rc setup erase command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh2 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address *2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il address (a 1 to a 18 ) d 8 to d 15 erase cycle 5: ce 1 = v ih : 8-bit bus organization : undefined
33 MB98A809Bx-/810bx-/811bx-/812bx- 25 main memory erase cycle timing diagram (ce = controlled) *1 notes: *1. a 0 , a 19 , a 20 and a 21 have to be ?ed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2. a 0 = either v il or v ih . data i n = 2020h data i n = 2020h data i n = a0a0h erase command erasing erase verify command erase verify t wc t wc t wc t ah t as t rc setup erase command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh2 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1 = ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a 0 , a 19 , a 20 , a 21 ) 12 v v ih v il address (a 1 to a 18 ) d 0 to d 15 erase cycle 6: ce 1 = ce 2 : 16-bit bus organization : undefined
34 MB98A809Bx-/810bx-/811bx-/812bx- 25 attribute memory write cycle timing diagram (we = controlled, reg = v il ) *1 notes: *1. this timing diagram is for MB98A809B3, 810b3, 811b3, and 812b3. ?f data is available on MB98A809B2, 810b2, 811b2, and 812b2 only. *2. data polling operation. write cycle 1: ce 2 = v ih : 8-bit bus organization ce 1 address (a 0 to a 11 ) high-z t rcs v ih v il v ih v il t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d 7 * 2 t rrbo t roes t rdh t rah t rre t roeh t rwr high-z i 7 oe we d 0 to d 7 o 7 : undefined
35 MB98A809Bx-/810bx-/811bx-/812bx- 25 attribute memory write cycle timing diagram (we = controlled, reg = v il ) *1 notes: *1. this timing diagram is for MB98A809B3, 810b3, 811b3, and 812b3. ?f data is available on MB98A809B2, 810b2, 811b2, and 812b2 only. *2. h-level or l-level is output from d 8 to d 15 . *3. data polling operation. write cycle 2: ce 1 = ce 2 : 16-bit bus organization : undefined we oe ce 1 = ce 2 high-z t rcs v ih v il v ih v il t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d 7 * 3 t rrbo t roes t rdh t rah t rre t roeh t rwr d 0 to d 7 * 2 high-z o 7 address (a 0 to a 11 ) i 7
36 MB98A809Bx-/810bx-/811bx-/812bx- 25 attribute memory write cycle timing diagram (ce = controlled, reg = v il ) *1 notes: *1. this timing diagram is for MB98A809B3, 810b3, 811b3, and 812b3. ?f data is available on MB98A809B2, 810b2, 811b2, and 812b2 only. *2. data polling operation. write cycle 3: ce 2 = v ih : 8-bit bus organization : undefined we oe ce 1 high-z t rcs v ih v il v ih v il t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d 7 * 2 t rrbo t roes t rdh t rah t rre t roeh t rwr high-z o 7 address (a 0 to a 11 ) d 0 to d 7 i 7
37 MB98A809Bx-/810bx-/811bx-/812bx- 25 attribute memory write cycle timing diagram (ce = controlled, reg = v il ) *1 notes: *1. this timing diagram is for MB98A809B3, 810b3, 811b3, and 812b3. ?f data is available on MB98A809B2, 810b2, 811b2, and 812b2 only. *2. h-level or l-level is output from d 8 to d 15 . *3. data polling operation. write cycle 4: ce 1 = ce 2 : 16-bit bus organization : undefined oe ce 1 = ce 2 high-z t rcs v ih v il v ih v il t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d 7 * 3 t rrbo t roes t rdh t rah t rre t roeh t rwr high-z o 7 we d 0 to d 7 * 2 address (a 0 to a 11 ) i 7
38 MB98A809Bx-/810bx-/811bx-/812bx- 25 n write/erase information fig. 4 ? write flowchart for 8-bit organization start v pph = 12.0 v 0.6 v v ppl 6.5 v s: start address g: address n: stop address x: counter value v cc = 5.0 v 0.25 v v pp1 = v pp2 = v pph yes write setup command = 40h g ? s yes no x ? 1 write data to card time out (10 m s) write verify command = c0h time out (6 m s) read data from card verify data x = 25? no x = x + 1 read command = 00h g = n? v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl end yes read command = 00h v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl error no g = g + 1
39 MB98A809Bx-/810bx-/811bx-/812bx- 25 fig. 5 ? write flowchart for 16-bit organization start v pph = 12.0 v 0.6 v v ppl 6.5 v s: start address g: address n: stop address xo: odd byte counter value xe: even byte counter value y: programming flag v cc = 5.0 v 0.25 v v pp1 = v pp2 = v pph yes write setup command = 4040h (when y = 0) = ff40h (when y = 1) = 40ffh (when y = 2) g ? s yes no xe ? 1, xo ? 1, y ? 0 time out (10 m s) write verify command = c0c0h (when y = 0) = 00c0h (when y = 1) = c000h (when y = 2) time out (6 m s) verify data xe = 25? or xo = 25? read command = 0000h g = n? v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl end yes v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl error no g = g + 2 write data to card = wdwdh (when y = 0) = ffwdh (when y = 1) = wdffh (when y = 2) read data from card read command = 0000h lower byte? yes y= 2 xo = xo + 1 no upper byte? yes y = 1 xe = xe + 1 no y = 0, xe = xe + 1 xo = xo + 1 no
40 MB98A809Bx-/810bx-/811bx-/812bx- 25 fig. 6 ? erase flowchart for 8-bit organization lower byte erase address set up (a 0 = 0) start v pph = 12.0 v 0.6 v v ppl 6.5 v g: address n1: lower byte end address n2: upper byte end address x: counter value v cc = 5.0 v 0.25 v v pp1 = v pp2 = v pph yes erase setup command = 20h no x ? 1 erase command = 20h time out (10 ms) erase verify command = a0h time out (6 m s) read data from card data = ffh? x = 3000? no x = x + 1 g = n1? no g = g + 2 yes 1 2 (continued on page 41.) (continued on page 41.) all data = 00h? write 00h to card yes
41 MB98A809Bx-/810bx-/811bx-/812bx- 25 v pph = 12.0 v 0.6 v v ppl 6.5 v g: address n1: lower byte end address n2: upper byte end address x: counter value fig. 7 ? erase flowchart for 8-bit organization (continued) yes erase setup command = 20h no x ? 1 erase command = 20h time out (10 ms) erase verify command = a0h time out (6 m s) read data from card data = ffh? x = 3000? yes x = x + 1 read command = 00h g = n2? v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl end no read command = 00h v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl error no g = g + 2 1 2 (continued from page 40.) (continued from page 40.) upper byte erase address setup (a 0 = 1) yes
42 MB98A809Bx-/810bx-/811bx-/812bx- 25 yes read command = 0000h fig. 8 ? erase flowchart for 16-bit organization write 0000h to card start v cc = 5.0 v 0.25 v v pph = 12.0 v 0.6 v v ppl 6.5 v g: address n: stop address xo: odd byte counter value xe: even byte counter value y: erasing flag yes erase setup command = 2020h (when y = 0) = ff20h (when y = 1) = 20ffh (when y = 2) no xe ? 1, xo ? 1, y ? 0 time out (10 ms) erase verify command = a0a0h (when y = 0) = 00a0h (when y = 1) = a000h (when y = 2) time out (6 m s) data = ffffh? xe = 3000? or xo = 3000? read command = 0000h g = n? end yes error no g = g + 2 erase command = 2020h (when y = 0) = ff20h (when y = 1) = 20ffh (when y = 2) read data from card lower byte? y = 2 xo = xo + 1 no upper byte? yes y = 1 xe = xe + 1 no v cc , v pp1 = v pp2 = v ppl v cc , v pp1 = v pp2 = v ppl y = 0, xe = xe + 1 xo = xo + 1 no v cc , v pp1 = v pp2 = v pph data = 0000h? erase address setup yes
43 MB98A809Bx-/810bx-/811bx-/812bx- 25 n unique features for flash memory card n device handling precautions this device in composed of ?e electronic parts, so take care in handling or keeping it as below. the card is made ?e, so do not keep it in the high temperature nor high humiditly, place like in the direct sun- shine nor near the heater. the card should not be bent, scratched, dropped nor be shocked violently. this device should never be taken a part. it could destroy the card or your personal computer hardware. to help you handle this device safely, request us the device speci?ations when purchasing this device. 1. special monitoring pins wp switch wp (output) protect h non protect l (a) (b) v cc cd 1 cd 2 system side card side ?fig. 10 ?fig. 9 1.1 cd 1 , cd 2 : card detection pins these pins detect the insertion of the card into the system. (see fig. 9.) when the memory card has been correctly inserted, cd 1 and cd 2 are detected by the system. cd 1 , cd 2 are tied to ground on the card side as shown in fig. 9. 1.2 wp: write protect pins this pin monitors the position of the write protect switch. as shown in fig. 10, the flash memory card has a write protect switch at the top of the card. to write to the card, the switch must be turned to the ?on protect position and the we pin low. l-level is output on the wp pin. to prevent writing to the card, the switch must be turned to the ?rotect?position. h-level is output on the wp pin. non protect flash memory card write protect switch v cc protect
44 MB98A809Bx-/810bx-/811bx-/812bx- 25 n package dimensions 68-pin memory card (case no.: crd-68p-m17) dimensions comform with pcmcia/jeida (pc card standard 95) "a" 1.600.05 (.063.002) 85.600.20(3.370.008) 10.50(.413) 10.50(.413) 2-r1.00(.039) 1.000.05 (.039.002) 1.000.05 (.039.002) 1.000.05 (.039.002) 3.300.10(.130.004) 1.270.10(.050.004)typ. 3.300.20(.130.008) 1pin 1.270.10 (.050.004) 41.91 ref (1.650) 54.000.10 (2.126.004) c 1994 fujitsu limited k68017sc-2-2 (.571) 14.50 details of "a" part dimensions in mm (inches) card body connector portion
45 MB98A809Bx-/810bx-/811bx-/812bx- 25 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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